EDN

Renesas halves memory chip size by merging SRAM and DRAM

TOKYO — Renesas Technology Corp. has developed a new SRAM memory cell combining SRAM and DRAM technologies. The new cell is about half the size of conventional SRAM cells but retains such advantages ...
EDN

Record SRAM Size, Non-Conventional Lithography, New Tunneling Transistor Highlight the Late-News Topics to be Covered at 2009 IEEE International Electron Devices Meeting

Record SRAM Size, Non-Conventional Lithography, New Tunneling Transistor Highlight the Late-News Topics to be Covered at 2009 IEEE International Electron Devices Meeting BALTIMORE, MD (October 26, ...
Semiconductor Engineering

TOPS, Memory, Throughput And Inference Efficiency

Dozens of companies have or are developing IP and chips for Neural Network Inference. Almost every AI company gives TOPS but little other information. What is TOPS? It means Trillions or Tera ...
Semiconductor Engineering

Overcoming Challenges In Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each ...