EDN

Layout compaction accelerates SoC design through hard IP reuse

In enabling multimillion-gate SoC designs, the latest process technologies have widened the gap between manufacturing capabilities and designers' abilities to quickly put together these complex ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
Semiconductor Engineering

Fast-Track Your Early SoC Design Exploration And Verification

Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as ...
Embedded

Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...
EDN

Altering the SOC-design flow

SOC (system-on-chip)-design teams at the leading edge of their markets say that “business as usual” is no longer the case. Powerful technical and business forces, seemingly independent of the EDA ...
Electronic Design

Plan Ahead For A Successful SoC-Based PCB Design

This file type includes high resolution graphics and schematics when applicable. In the development of SoC-based (system-on-chip) circuit boards, the SoC’s additional capabilities will provide ...
Electronic Design

Renesas’ Cockpit Reference Design is Based on its R-Car SoC

Renesas Electronics developed a reference solution for digital cockpit applications that’s based on the R-Car M3 system-on-chip (SoC). The Renesas Cockpit Reference Solution employs module-level ...